Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-214116, filed on Sep. 16,2009; the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Field

Embodiments of this invention relate generally to a nonvolatilesemiconductor memory device.

2. Background Art

A method for collectively processing a three-dimensional multilayermemory has been proposed to increase the memory capacity of anonvolatile semiconductor memory device (memory) (see, e.g., JP-A2007-266143 (Kokai)). In this method, a multilayer memory can becollectively formed irrespective of the number of stacked layers, andhence the increase of cost can be suppressed.

In this collectively processed three-dimensional multilayer memory,insulating films and electrode films (to serve as word lines) arealternately stacked to form a multilayer body, in which through holesare collectively provided. Then, a charge storage layer (memory layer)is provided on the side surface of the through hole, and silicon isfilled inside the through hole to form a silicon pillar. A tunnelinsulating film is provided between the charge storage layer and thesilicon pillar, and a block insulating film is provided between thecharge storage layer and the electrode film. Thus, a memory cellillustratively made of a MONOS (metal oxide nitride oxide semiconductor)transistor is formed at the intersection between each of the electrodefilms and the silicon pillar.

In such a collectively processed three-dimensional multilayer memory,further stabilization of its erase state has many advantages, such ashigher controllability in the write operation.

A method of performing a plurality of erase loops as the erase operationhas been proposed for a three-dimensional multilayer memory with planarmemory cells simply stacked therein, not for the collectively processedthree-dimensional multilayer memory as described above. However, becausethe structure and operating mechanism of memory cells are different fromthose in the collectively processed three-dimensional multilayer memory,this method is not directly applicable to the collectively processedthree-dimensional multilayer memory. Thus, it is necessary to develop anoperation method specific to the collectively processedthree-dimensional multilayer memory.

SUMMARY

According to an aspect of the invention, there is provided a nonvolatilesemiconductor memory device including: a memory unit; and a controlunit, the memory unit including: a multilayer structure including aplurality of electrode films and a plurality of interelectrodeinsulating films alternately stacked in a first direction; a firstsemiconductor pillar piercing the multilayer structure in the firstdirection; a first memory layer provided between each of the electrodefilms and the first semiconductor pillar; a first inner insulating filmprovided between the first memory layer and the first semiconductorpillar; a first outer insulating film provided between each of theelectrode films and the first memory layer; and a first wiringelectrically connected to one end of the first semiconductor pillar, thecontrol unit performing: a first operation setting the first wiring at afirst potential and setting the electrode film at a second potentiallower than the first potential during a first period; and an operationincluding a second operation setting the first wiring at a thirdpotential and setting the electrode film at a fourth potential lowerthan the third potential during a second period after the firstoperation, the operation including the second operation having at leastone of: a length of the second period being shorter than a length of thefirst period; and a difference between the third potential and thefourth potential being smaller than a difference between the firstpotential and the second potential, the first operation and theoperation including the second operation being performed in an operationfor performing at least one of injection of holes into the first memorylayer and extraction of electrons from the first memory layer.

According to another aspect of the invention, there is provided anonvolatile semiconductor memory device including: a memory unit; and acontrol unit, the memory unit including: a multilayer structureincluding a plurality of electrode films and a plurality ofinterelectrode insulating films alternately stacked in a firstdirection; a semiconductor pillar piercing the multilayer structure inthe first direction; a memory layer provided between each of theelectrode films and the semiconductor pillar; an inner insulating filmprovided between the memory layer and the semiconductor pillar; an outerinsulating film provided between each of the electrode films and thememory layer; and a wiring electrically connected to one end of thesemiconductor pillar, and the control unit setting: the wiring at afirst potential; and the electrode film opposed to one of memorysections of the memory layer facing the plurality of electrode films ata second potential lower than the first potential and the electrode filmopposed to the memory section except the one of memory sections in afloating state, the setting being performed in an operation forperforming at least one of injection of holes into the one memorysection and extraction of electrons from the one memory section.

According to another aspect of the invention, there is provided anonvolatile semiconductor memory device including: a memory unit; and acontrol unit, the memory unit including: a multilayer structureincluding a plurality of electrode films and a plurality ofinterelectrode insulating films alternately stacked in a firstdirection; a semiconductor pillar piercing the multilayer structure inthe first direction; a memory layer provided between each of theelectrode films and the semiconductor pillar; an inner insulating filmprovided between the memory layer and the semiconductor pillar; an outerinsulating film provided between each of the electrode films and thememory layer; and a wiring electrically connected to one end of thesemiconductor pillar, and the control unit setting: the wiring at afirst potential one electrode film of the plurality of electrode filmsat a second potential lower than the first potential; and anotherelectrode film of the plurality of electrode films at a seventhpotential lower than the first potential and different from the secondpotential, the setting being performed in an operation for performing atleast one of injection of holes into the memory layer and extraction ofelectrons from the memory layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating the operation of a nonvolatilesemiconductor memory device according to a first embodiment;

FIG. 2 is a schematic cross-sectional view illustrating theconfiguration of the nonvolatile semiconductor memory device accordingto the first embodiment;

FIG. 3 is a schematic perspective view illustrating the configuration ofthe nonvolatile semiconductor memory device according to the firstembodiment;

FIG. 4 is a schematic cross-sectional view illustrating theconfiguration of the nonvolatile semiconductor memory device accordingto the first embodiment;

FIG. 5 is a schematic plan view illustrating the configuration of theelectrode films of the nonvolatile semiconductor memory device accordingto the first embodiment;

FIGS. 6A to 6D are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment;

FIGS. 7A to 7C are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment;

FIGS. 8A to 8C are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment;

FIGS. 9A to 9D are schematic diagrams illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment.

FIGS. 10A to 10C are schematic diagrams illustrating the operation ofthe alternative nonvolatile semiconductor memory device according to thefirst embodiment;

FIGS. 11A and 11B are flow charts illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment;

FIGS. 12A to 12D are schematic diagrams illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment;

FIGS. 13A to 13D are schematic diagrams illustrating the operation of anonvolatile semiconductor memory device according to a secondembodiment;

FIGS. 14A to 14F are schematic diagrams illustrating the operation of anonvolatile semiconductor memory device according to a third embodiment;

FIG. 15 is a schematic cross-sectional view illustrating theconfiguration of a nonvolatile semiconductor memory device according toa fourth embodiment; and

FIG. 16 is a schematic perspective view illustrating the configurationof the nonvolatile semiconductor memory device according to the fourthembodiment.

DETAILED DESCRIPTION

Embodiments of the invention will now be described with reference to thedrawings.

The drawings are schematic or conceptual. The relationship between thethickness and the width of each portion, and the size ratio between theportions, for instance, are not necessarily identical to those inreality. Furthermore, the same portion may be shown with differentdimensions or ratios depending on the figures.

In the specification and the drawings, the same elements as thosedescribed previously with reference to earlier figures are labeled withlike reference numerals, and the detailed description thereof is omittedas appropriate.

First Embodiment

FIG. 1 is a flow chart illustrating the operation of a nonvolatilesemiconductor memory device according to a first embodiment.

FIGS. 2, 3, and 4 are a schematic cross-sectional view, a schematicperspective view, and a schematic cross-sectional view, respectively,illustrating the configuration of the nonvolatile semiconductor memorydevice according to the first embodiment.

It is noted that for clarity of illustration, FIG. 3 shows only theconductive portions and omits the insulating portions.

FIG. 5 is a schematic plan view illustrating the configuration of theelectrode films of the nonvolatile semiconductor memory device accordingto the first embodiment.

A nonvolatile semiconductor memory device 110 according to thisembodiment is a collectively processed three-dimensional multilayermemory.

First, the configuration of the nonvolatile semiconductor memory device110 is outlined with reference to FIGS. 2 to 5.

As shown in FIG. 2, the nonvolatile semiconductor memory device 110includes a memory unit MU and a control unit CTU. The memory unit MU andthe control unit CTU are provided on the major surface 11 a of asubstrate 11 illustratively made of single crystal silicon. However, thecontrol unit CTU may be provided on a substrate different from thesubstrate on which the memory unit MU is provided. In the followingdescription, it is assumed that the memory unit MU and the control unitCTU are provided on the same substrate (substrate 11).

On the substrate 11, for instance, a memory array region MR to beprovided with memory cells and a peripheral region PR illustrativelyprovided around the memory array region MR are defined. In theperipheral region PR, various peripheral region circuits PR1 areprovided on the substrate 11.

In the memory array region MR, a circuit unit CU is illustrativelyprovided on the substrate 11, and the memory unit MU is provided on thecircuit unit CU. It is noted that the circuit unit CU is provided asneeded and can be omitted. An interlayer insulating film 13illustratively made of silicon oxide is provided between the circuitunit CU and the memory unit MU.

At least part of the control unit CTU, for instance, can illustrativelybe provided in at least one of the peripheral region circuit PR1 and thecircuit unit CU described above.

The memory unit MU includes a matrix memory cell unit MU1 including aplurality of memory transistors MT and a wiring connecting unit MU2 forconnecting wirings in the matrix memory cell unit MU1.

FIG. 3 illustrates the configuration of the matrix memory cell unit MU1.

With regard to the matrix memory cell unit MU1, FIG. 2 illustrates partof the A-A′ cross section of FIG. 3 and part of the B-B′ cross sectionof FIG. 3.

As shown in FIGS. 2 and 3, in the matrix memory cell unit MU1, amultilayer structure ML is provided on the major surface 11 a of thesubstrate 11. The multilayer structure ML includes a plurality ofelectrode films WL and a plurality of interelectrode insulating films 14alternately stacked in the direction perpendicular to the major surface11 a.

In this specification, for convenience of description, an XYZ orthogonalcoordinate system is introduced. In this coordinate system, thedirection perpendicular to the major surface 11 a of the substrate 11 isreferred to as a Z-axis direction (first direction). Furthermore, one ofthe directions in the plane parallel to the major surface 11 a isreferred to as a Y-axis direction (second direction). Furthermore, thedirection perpendicular to the Z axis and the Y axis is referred to as aX-axis direction (third direction).

The stacking direction of the electrode films WL and the interelectrodeinsulating films 14 in the multilayer structure ML is the Z-axisdirection. In other words, the electrode films WL and the interelectrodeinsulating films 14 are provided parallel to the major surface 11 a.

FIG. 4 illustrates the configuration of the matrix memory cell unit MU1,illustratively corresponding to part of the B-B′ cross section of FIG.3.

As shown in FIGS. 3 and 4, the memory unit MU of the nonvolatilesemiconductor memory device 110 includes the aforementioned multilayerstructure ML, a semiconductor pillar SP (first semiconductor pillar SP1)piercing the multilayer structure ML in the Z-axis direction, a memorylayer 48 (first memory layer 48 a), an inner insulating film 42 (firstinner insulating film 42 a), an outer insulating film 43 (first outerinsulating film 43 a), and a wiring WR (first wiring W1).

The memory layer 48 is provided between each of the electrode films WLand the semiconductor pillar SP. The inner insulating film 42 isprovided between the memory layer 48 and the semiconductor pillar SP.The outer insulating film 43 is provided between each of the electrodefilms WL and the memory layer 48. The wiring WR is electricallyconnected to one end (first end) of the semiconductor pillar SP.

For instance, the outer insulating film 43, the memory layer 48, and theinner insulating film 42 are formed in this order on the inner wallsurface of the through hole TH piercing the multilayer structure ML inthe Z-axis direction, and the remaining space is filled with asemiconductor to form the semiconductor pillar SP.

A memory cell MC is provided at the intersection between the electrodefilm WL of the multilayer structure ML and the semiconductor pillar SP.That is, memory transistors MT including the memory layer 48 areprovided in a three-dimensional matrix at the intersection between theelectrode film WL and the semiconductor pillar SP. Each of the memorytransistors MT functions as a memory cell MC for storing data by storingcharge in the memory layer 48.

The inner insulating film 42 functions as a tunnel insulating film inthe memory transistor MT of the memory cell MC. On the other hand, theouter insulating film 43 functions as a block insulating film in thememory transistor MT of the memory cell MC. The interelectrodeinsulating film 14 functions as an interlayer insulating film forinsulating the electrode films WL from each other.

The electrode film WL can be made of any conductive material, such asamorphous silicon or polysilicon provided with conductivity by impuritydoping, or can be made of metals and alloys. A prescribed electricalsignal is applied to the electrode film WL, which functions as a wordline of the nonvolatile semiconductor memory device 110.

The interelectrode insulating film 14, the inner insulating film 42, andthe outer insulating film 43 can illustratively be silicon oxide films.It is noted that the interelectrode insulating film 14, the innerinsulating film 42, and the outer insulating film 43 may be a monolayerfilm or a multilayer film.

The memory layer 48 can illustratively be a silicon nitride film andfunctions as a portion for storing information by storing or releasingcharge by an electric field applied between the semiconductor pillar SPand the electrode film WL. The memory layer 48 may be a monolayer filmor a multilayer film.

As described later, the interelectrode insulating film 14, the innerinsulating film 42, the memory layer 48, and the outer insulating film43 can be made of various materials, not limited to the materialsillustrated above.

Although FIGS. 2 and 3 illustrate the case where the multilayerstructure ML includes four electrode films WL, the number of electrodefilms WL provided in the multilayer structure ML is arbitrary. In thefollowing description, it is assumed that the number of electrode filmsWL is four.

In this example, two semiconductor pillars SP are connected by aconnecting portion CP. More specifically, the memory unit MU furtherincludes a second semiconductor pillar SP2 (one of a plurality ofsemiconductor pillars SP), a second memory layer 48 b, a second innerinsulating film 42 b, a second outer insulating film 43 b, a secondwiring W2, a first connecting portion CP1 (one of a plurality ofconnecting portions CP), a first select gate SG1 (one of a plurality ofselect gates SG, such as source side select gate SGS), and a secondselect gate SG2 (one of the plurality of select gates SG, such as drainside select gate SGD).

The second semiconductor pillar SP2 is adjacent to the firstsemiconductor pillar SP1 (one of the plurality of semiconductor pillarsSP) illustratively in the Y-axis direction and pierces the multilayerstructure ML in the Z-axis direction.

The second memory layer 48 b is provided between each of the electrodefilms WL and the second semiconductor pillar SP2. The second innerinsulating film 42 b is provided between the second memory layer 48 band the second semiconductor pillar SP2. The second outer insulatingfilm 43 b is provided between each of the electrode films WL and thesecond memory layer 48 b.

The second wiring WR2 is electrically connected to one end (second end)of the second semiconductor pillar SP2.

The first connecting portion CP1 electrically connects the other end(third end) opposite to the one end (first end) of the firstsemiconductor pillar SP1 and the other end (fourth end) opposite to theone end (second end) of the second semiconductor pillar SP2.

Specifically, the third end is the end of the first semiconductor pillarSP1 on the substrate 11 side, and the fourth end is the end of thesecond semiconductor pillar SP2 on the substrate 11 side. The firstconnecting portion CP1 connects the first semiconductor pillar SP1 andthe second semiconductor pillar SP2 to each other on the substrate 11side. The first connecting portion CP1 aligns in the Y-axis direction.The first connecting portion CP1 is made of the same material as thefirst and second semiconductor pillars SP1 and SP2.

More specifically, a back gate BG (connecting conductive layer) isprovided on the major surface 11 a of the substrate 11 via theinterlayer insulating film 13. A trench is provided in portions of theback gate BG opposed to the first and second semiconductor pillars SP1and SP2. An outer insulating film 43, a memory layer 48, and an innerinsulating film 42 are formed inside the trench, and the remaining spaceis filled with a connecting portion CP made of a semiconductor. It isnoted that the formation of the outer insulating film 43, the memorylayer 48, the inner insulating film 42, and the connecting portion CP inthe trench is performed simultaneously and collectively with theformation of the outer insulating film 43, the memory layer 48, theinner insulating film 42, and the semiconductor pillar SP. Thus, theback gate BG is provided opposite to the connecting portion CP.

Thus, the first and second semiconductor pillars SP1 and SP2 and theconnecting portion CP constitute a U-shaped memory string. This memorystring is illustratively a NAND memory string.

However, the invention is not limited thereto. As described later, eachsemiconductor pillar SP may be independent and not be connected by theconnecting portion CP on the substrate 11 side. In the followingdescription, it is assumed that two semiconductor pillars SP areconnected by the connecting portion CP.

As shown in FIGS. 2 and 3, one end (first end) of the firstsemiconductor pillar SP1 opposite to the first connecting portion CP1 isconnected to a source line SL (first wiring W1), and one end (secondend) of the second semiconductor pillar SP2 opposite to the firstconnecting portion CP1 is connected to a bit line BL (second wiring W2).Here, the semiconductor pillar SP is connected to the bit line BL by avia VA1 and a via VA2.

In this example, the bit line BL aligns in the Y-axis direction, and thesource line SL aligns in the X-axis direction.

The first select gate SG1 (e.g., source side select gate SGS) isprovided between the first end of the first semiconductor pillar SP1 andthe multilayer structure ML and pierced by the first semiconductorpillar SP1.

The second select gate SG2 (e.g., drain side select gate SGD) isprovided between the second end of the second semiconductor pillar SP2and the multilayer structure ML and pierced by the second semiconductorpillar SP2.

Thus, desired data can be written to and read from an arbitrary memorycell MC of an arbitrary semiconductor pillar SP.

The select gate SG can be made of any conductive material, such aspolysilicon or amorphous silicon. In this example, the select gate SG isdivided in the Y-axis direction and shaped like strips aligning in theX-axis direction.

As shown in FIG. 2, an interlayer insulating film 15 is provided at thetop (on the side farthest from the substrate 11) of the multilayerstructure ML. Furthermore, an interlayer insulating film 16 is providedon the multilayer structure ML, a select gate SG is provided thereon,and an interlayer insulating film 17 is provided between the selectgates SG. A through hole TH is provided in the select gate SG, a selectgate insulating film SGI of a select gate transistor is provided on theinner side surface thereof, and a semiconductor is filled inside it.This semiconductor is connected to the semiconductor pillar SP.

That is, the memory unit MU includes a select gate SG stacked on themultilayer structure ML in the Z-axis direction and pierced by thesemiconductor pillar SP on the wiring WR (at least one of the sourceline SL and the bit line BL) side.

Furthermore, an interlayer insulating film 18 is provided on theinterlayer insulating film 17, and a source line SL and vias 22 (viasVA1 and VA2) are provided thereon, and an interlayer insulating film 19is provided around the source line SL. Furthermore, an interlayerinsulating film 23 is provided on the source line SL, and a bit line BLis provided thereon.

The interlayer insulating films 15, 16, 17, 18, 19, and 23, and theselect gate insulating film SGI can illustratively be made of siliconoxide.

With regard to the plurality of semiconductor pillars provided in thenonvolatile semiconductor memory device 110, when all or any of thesemiconductor pillars are referred to, the wording “semiconductor pillarSP” is used. On the other hand, when a particular semiconductor pillaris referred to in describing the relationship between the semiconductorpillars, for instance, the wording “n-th semiconductor pillar SPn” (n isany integer of one or more) is used.

As shown in FIG. 5, among the electrode films WL, the electrode filmscorresponding to the semiconductor pillars SP(4m+1) and SP(4m+3) withthe aforementioned integer n being equal to 4m+1 and 4m+3 are commonlyconnected into an electrode film WLA, and the electrode filmscorresponding to the semiconductor pillars SP(4m+2) and SP(4m+4) with nbeing equal to 4m+2 and 4m+4 are commonly connected into an electrodefilm WLB, where m is an integer of zero or more. That is, the electrodefilms WL are shaped into the electrode film WLA and the electrode filmWLB, which are opposed in the X-axis direction and meshed with eachother like comb teeth.

As shown in FIGS. 4 and 5, the electrode film WL is divided by aninsulating layer IL into a first region (electrode film WLA) and asecond region (electrode film WLB).

Furthermore, as in the wiring connecting unit MU2 illustrated in FIG. 2,at one end in the X-axis direction, the electrode film WLB is connectedto a word line 32 by a via plug 31 and electrically connected to, forinstance, a driving circuit provided in the substrate 11. Likewise, atthe other end in the X-axis direction, the electrode film WLA isconnected to the word line by the via plug and electrically connected tothe driving circuit. In other words, the length in the X-axis directionof the electrode films WL (electrode film WLA and electrode film WLB)stacked in the Z-axis direction is varied stepwise, so that electricalconnection to the driving circuit is implemented by the electrode filmWLA at one end in the X-axis direction and by the electrode film WLB atthe other end in the X-axis direction.

As shown in FIG. 3, the memory unit MU can further include a thirdsemiconductor pillar SP3 (one of the plurality of semiconductor pillarsSP), a fourth semiconductor pillar SP4 (one of the plurality ofsemiconductor pillars SP), and a second connecting portion CP2 (one ofthe plurality of connecting portions CP).

The third semiconductor pillar SP3 is adjacent to the firstsemiconductor pillar SP1 on the opposite side of the first semiconductorpillar SP1 from the second semiconductor pillar SP2 in the Y-axisdirection and pierces the multilayer structure ML in the Z-axisdirection. The fourth semiconductor pillar SP4 is adjacent to the thirdsemiconductor pillar SP3 on the opposite side of the third semiconductorpillar SP3 from the first semiconductor pillar SP1 in the Y-axisdirection and pierces the multilayer structure ML in the Z-axisdirection.

The second connecting portion CP2 electrically connects the thirdsemiconductor pillar SP3 and the fourth semiconductor pillar SP4 on thesame side (the same side as the first connecting portion CP1) in theZ-axis direction. The second connecting portion CP2 aligns in the Y-axisdirection and is opposed to the back gate BG.

The memory layer 48 is provided also between each of the electrode filmsWL and the third and fourth semiconductor pillars SP3 and SP4 andbetween the back gate BG and the second connecting portion CP2. Theinner insulating film 42 is provided also between the third and fourthsemiconductor pillars SP3 and SP4 and the memory layer 48 and betweenthe memory layer 48 and the second connecting portion CP2. The outerinsulating film 43 is provided also between each of the electrode filmsWL and the memory layer 48 and between the memory layer 48 and the backgate BG.

The source line SL is connected to the end of the third semiconductorpillar SP3 opposite to the second connecting portion CP2. The bit lineBL is connected to the end of the fourth semiconductor pillar SP4opposite to the second connecting portion CP2.

Furthermore, a third select gate SG3 (one of the plurality of selectgates SG, such as source side select gate SGS) is provided opposite tothe third semiconductor pillar SP3, and a fourth select gate SG4 (one ofthe plurality of select gates SG, such as drain side select gate SGD) isprovided opposite to the fourth semiconductor pillar SP4.

As shown in FIG. 1, in the nonvolatile semiconductor memory device 110thus configured, when performing an erase operation, the control unitCTU performs operations including execution of a first operation E1(step S110) and execution of a second operation E2 (step S120) describedbelow.

The first operation E1 (first erase operation) is performed during afirst period. In the first operation E1, the control unit CTU sets thefirst wiring W1 at a first potential V01 and the electrode film WL at asecond potential V02 lower than the first potential V01.

The second operation E2 (second erase operation) is performed during asecond period after the first operation E1. In the second operation E2,the control unit CTU sets the first wiring W1 at a third potential V03and the electrode film WL at a fourth potential V04 lower than the thirdpotential V03.

Furthermore, at least one of the following is satisfied: the length ofthe second period being shorter than the length of the first period; andthe difference between the third potential V03 and the fourth potentialV04 being lower than the difference between the first potential V01 andthe second potential V02.

The erase operation is the operation of performing at least one ofinjection of holes into the memory layer 48 (first memory layer 48 a andsecond memory layer 48 b) and extraction of electrons from the memorylayer 48 (first memory layer 48 a and second memory layer 48 b). Thememory transistor MT serving as a memory cell MC has a state (erasestate) of low threshold voltage and a state (write state) having arelatively higher threshold voltage than the state of low thresholdvoltage. The erase operation is an operation for setting the thresholdvoltage of the memory transistor MT to the lower state.

The write operation is the operation of performing at least one ofinjection of electrons into the memory layer 48 and extraction of holesfrom the memory layer 48. That is, the write operation is an operationfor setting the threshold voltage of the memory transistor MT to thehigher state.

In the first operation E1, because the second potential V02 is lowerthan the first potential V01, the electrode film WL is set at apotential of negative polarity with reference to the first wiring W1.This results in performing at least one of injection of holes into thememory layer 48 and extraction of electrons from the memory layer 48.

The first operation E1 is the erase operation. The first operation E1produces a state (shallow state) having a voltage slightly higher thanthe target threshold voltage. That is, the first operation E1 is “softerasure”.

In the second operation E2 as well, because the fourth potential V04 islower than the third potential V03, the electrode film WL is set at apotential of negative polarity with reference to the first wiring W1.This results in performing at least one of injection of holes into thememory layer 48 and extraction of electrons from the memory layer 48.

The second operation E2 is also the erase operation. The thresholdvoltage, which has been set slightly higher than the target thresholdvoltage in the first operation E1, is set to the target value by thissecond operation E2. That is, the second operation E2 is “additionalerasure”.

For instance, the length of the second period of the second operation E2is set shorter than the length of the first period of the firstoperation E1. In other words, the pulse width of the erase voltageapplied in the second operation E2 is set shorter than the pulse widthof the erase voltage applied in the first operation E1. Alternatively,the difference between the third potential V03 and the fourth potentialV04 is set smaller than the difference between the first potential V01and the second potential V02.

That is, the second operation E2 (additional erasure) is an operationwith at least one of shorter pulse width and lower erase voltage than inthe first operation E1 (soft erasure).

Thus, in the erase operation, a stable erase state can be realized bycombining the erase operation of “soft erasure” (first operation E1) forsetting the threshold voltage to a value higher (shallower) than thetarget value and the operation of “additional erasure” (second operationE2) for subsequently setting the threshold voltage to the target value.

In the following, for simplicity of description, a description is firstgiven of an example in which the length of the second period of thesecond operation E2 is equal to the length of the first period of thefirst operation E1 and the difference between the third potential V03and the fourth potential V04 is smaller than the difference between thefirst potential V01 and the second potential V02.

FIGS. 6A to 6D are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment. More specifically, FIGS. 6A and 6B are a schematic diagramand a graph, respectively, illustrating the state of potential in thefirst operation E1. FIGS. 6C and 6D are a schematic diagram and a graph,respectively, illustrating the state of potential in the secondoperation E2. In FIGS. 6B and 6D, the horizontal axis represents time t,and the vertical axis represents potential Vp.

FIGS. 7A to 7C are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment. More specifically, FIGS. 7A, 7B, and 7C show, in the firstoperation E1 and the second operation E2, the potential of the firstwiring W1 (the potential VSL of the source line SL) and the potential ofthe second wiring W2 (the potential VBL of the bit line BL); thepotential VSGD of the drain side select gate SGD and the potential VSGSof the source side select gate SGS; and the potential VWL of theelectrode film WL, respectively.

FIGS. 8A to 8C are schematic diagrams illustrating the operation of thenonvolatile semiconductor memory device according to the firstembodiment. More specifically, FIGS. 8A, 8B, and 8C are energy banddiagrams in the first operation E1, in the second operation E2, andafter the second operation E2, respectively.

As shown in FIGS. 6A and 6B, the control unit CTU sets the wiring WR(e.g., first wiring W1 and second wiring W2) at a first potential V01and the electrode film WL at a second potential V02 lower than the firstpotential V01. In the following, it is assumed that the second potentialV02 is the reference potential V00.

The reference potential V00 can be set to an arbitrary potential. In thefollowing, it is assumed that the reference potential V00 is the groundpotential GND.

For instance, as shown in FIGS. 7A to 7C, in the first operation E1, thefirst erase voltage Vera1 applied to the wiring WR rises from thereference potential V00 at time t11, reaches the first potential V01 attime t13, then keeps the first potential V01 until time t14, startsfalling at time t14, and returns to the reference potential V00 at timet16. In this example, the period from time t13 to time t14 is the firstperiod TE1.

The first erase-time select gate voltage VeraG1 applied to the sourceside select gate SGS and the drain side select gate SGD rises from thereference potential V00 at time t12, reaches a fifth potential V05 attime t13, then keeps the fifth potential V05 until time t14, startsfalling at time t14, and returns to the reference potential V00 at timet15.

In this example, the time when the first erase-time select gate voltageVeraG1 reaches the fifth potential V05 and the time when it startsfalling from the fifth potential V05 are respectively the same as thetime t13 when the first erase voltage Vera1 reaches the first potentialV01 and the time t14 when it starts falling from the first potentialV01. However, the time of reaching the fifth potential V05 and the timeof starting falling from the fifth potential V05 may be different fromthe time t13 of reaching the first potential V01 and the time t14 ofstarting falling from the first potential V01.

In the first operation E1, the potential of the electrode film WL andthe back gate BG is constant at the second potential V02 (referencepotential V00).

The first potential V01 is illustratively 20 V (volts), the fifthpotential V05 is illustratively 15 V, and the second potential V02(reference potential V00) is illustratively 0 V. Thus, the fifthpotential V05 is lower than the first potential V01, and the differencebetween the first potential V01 and the fifth potential V05 isillustratively about 5 V. It is noted that the maximum of the firsterase-time select gate voltage VeraG1 (i.e., the difference between thefifth potential V05 and the reference potential V00) is lower than thebreakdown voltage of the select gate transistor of the select gate SG.

Time t12 comes after time t11, time t13 comes after time t12, time t14comes after time t13, time t15 comes after time t14, and time t16 comesafter time t15.

The first erase voltage Vera1 is not less than the first erase-timeselect gate voltage VeraG1 at any time. More specifically, during thefirst period TE1, after the time (time t11) when the potential of thefirst wiring W1 starts changing from the second potential V02 to thefirst potential V01, the potential of the select gate (source sideselect gate SGS and drain side select gate SGD) starts changing from thesecond potential V02 to the fifth potential V05 (time t12). During thesecond period TE2, after the time (time t16) when the potential of thefirst wiring W1 finishes changing from the first potential V01 to thesecond potential V02, the potential of the select gate finishes changingfrom the fifth potential V05 to the second potential V02 (time t15).

By applying this first erase-time select gate voltage VeraG1 to thedrain side select gate SGD and the source side select gate SGS, GIDL(gate-induced drain leakage) can be generated in the semiconductorpillar SP near the portion opposed to the drain side select gate SGD andthe source side select gate SGS without gate breakdown of the selectgate transistor.

By applying the first erase voltage Vera1 to the first wiring W1 and thesecond wiring W2, holes are injected into the memory layer 48 (firstmemory layer 48 a and second memory layer 48 b) of the memory transistorMT formed at the intersection between the electrode film WL and thesemiconductor pillar SP. Here, the first erase voltage Vera1 is set to avoltage such that the threshold voltage of the memory transistor MT isslightly higher than the target value of the erase state. For instance,when the target threshold voltage is −2 V, the threshold voltage of thememory transistor MT is set to approximately −1 V. That is, soft erasureis performed.

In the erase operation, the operation based on GIDL as described aboveis specific to the collectively processed three-dimensional multilayermemory, unlike the operation in the three-dimensional multilayer memorywith planar memory cells simply stacked therein. Furthermore, in orderto generate GIDL, the aforementioned potential (first erase voltageVera1) of the wiring WR (first wiring W1 and second wiring W2) and theaforementioned potential (first erase-time select gate voltage VeraG1)of the select gate SG (first select gate SG1 and second select gate SG2)are specific to the collectively processed three-dimensional multilayermemory, unlike those in the three-dimensional multilayer memory withplanar memory cells simply stacked therein. Thus, the control unit CTUof the nonvolatile semiconductor memory device 110 according to thisembodiment performs operations specific to the collectively processedthree-dimensional multilayer memory.

Thus, as shown in FIG. 8A, holes are injected from the semiconductorpillar SP side toward the electrode film WL, and holes cg2 a arecaptured in the memory layer 48.

Here, the first erase voltage Vera1 is set to make the threshold voltageof the memory transistor MT shallower (higher) than the target thresholdvoltage. This suppresses holes cg2 b from being captured by traps atshallow energy levels at the interface between the semiconductor pillarSP and the inner insulating film 42 and in the portion of the innerinsulating film 42 on the semiconductor pillar SP side.

Subsequently, as shown in FIGS. 6C and 6D, in the second operation E2,the control unit CTU sets the wiring WR (e.g., first wiring W1 andsecond wiring W2) at a third potential V03 and the electrode film WL ata fourth potential V04 lower than the third potential V03. Here, thefourth potential V04 is arbitrary. However, in the following, it isassumed that the fourth potential V04 is equal to the second potentialV02 (i.e., in this example, the reference potential V00).

Because the difference between the third potential V03 and the fourthpotential V04 is smaller than the difference between the first potentialV01 and the second potential V02, the third potential V03 is lower thanthe first potential V01. The third potential V03 is illustratively 18 V.

For instance, as shown in FIGS. 7A to 7C, in the second operation E2,the second erase voltage Vera2 applied to the wiring WR rises from thereference potential V00 at time t21, reaches the third potential V03 attime t23, then keeps the third potential V03 until time t24, startsfalling at time t24, and returns to the reference potential V00 at timet26. In this example, the period from time t23 to time t24 is the secondperiod TE2. The length of the second period TE2 is equal to the lengthof the first period TE1.

The second erase-time select gate voltage VeraG2 applied to the sourceside select gate SGS and the drain side select gate SGD rises from thereference potential V00 at time t22, reaches a sixth potential V06 attime t23, then keeps the sixth potential V06 until time t24, startsfalling at time t24, and returns to the reference potential V00 at timet25. Again, the time of reaching the sixth potential V06 and the time ofstarting falling from the sixth potential V06 may be different from thetime t23 of reaching the third potential V03 and the time t24 ofstarting falling from the third potential V03, respectively.

In the second operation E2, the potential of the electrode film WL andthe back gate BG is constant at the fourth potential V04, which is equalto the second potential V02 or the reference potential V00.

If the third potential V03 is illustratively 18 V, the sixth potentialV06 is illustratively 13 V. The sixth potential V06 only needs to belower than the third potential V03 and higher than the fourth potentialV04 (in this example, the second potential V02, or the referencepotential V00) and may be equal to the fifth potential V05.

The sixth potential V06 is lower than the third potential V03. In thisexample, the difference between the third potential V03 and the sixthpotential V06 is approximately 5 V. Again, the maximum of the seconderase-time select gate voltage VeraG2 (i.e., the difference between thesixth potential V06 and the reference potential V00) is lower than thebreakdown voltage of the select gate transistor of the select gate SG.

Time t22 comes after time t21, time t23 comes after time t22, time t24comes after time t23, time t25 comes after time t24, and time t26 comesafter time t25.

The second erase voltage Vera2 is not less than the second erase-timeselect gate voltage VeraG2 at any time.

By applying this second erase-time select gate voltage VeraG2 to thedrain side select gate SGD and the source side select gate SGS, GIDL isgenerated in the semiconductor pillar SP near the portion opposed to thedrain side select gate SGD and the source side select gate SGS withoutgate breakdown of the select gate transistor.

By applying the second erase voltage Vera2 to the first wiring W1 andthe second wiring W2, holes are injected into the memory layer 48 (firstmemory layer 48 a and second memory layer 48 b) of the memory transistorMT.

Here, the second erase voltage Vera2 is set lower than the first erasevoltage Vera1. Thus, the threshold voltage, which has been set slightlyhigher by application of the first erase voltage Vera1, is slightlylowered and set to the target value. Consequently, the threshold voltageof the memory transistor MT is set to the target value, such as −2 V.

More specifically, as shown in FIG. 8B, holes are injected from thesemiconductor pillar SP side toward the electrode film WL, and holes cg2a are captured in the memory layer 48 in addition to the holes cg2 acaptured in the first operation E1.

Here, the second erase voltage Vera2 applied is a low voltage. This alsosuppresses holes cg2 b from being captured by traps at shallow energylevels at the interface between the semiconductor pillar SP and theinner insulating film 42 and in the portion of the inner insulating film42 on the semiconductor pillar SP side.

Thus, as shown in FIG. 8C, holes cg2 b are suppressed from beingcaptured by traps at shallow energy levels at the interface between thesemiconductor pillar SP and the inner insulating film 42 and in theportion of the inner insulating film 42 on the semiconductor pillar SPside. This results in the desired erase state in which holes cg2 a arecaptured in the memory layer 48.

By this second operation E2, the threshold voltage of the memorytransistor MT falls approximately 1 V from after the first operation E1and results in reaching the target value (e.g., −2 V).

Thus, in the nonvolatile semiconductor memory device 110 according tothis embodiment, the erase operation EP includes a combination of thefirst operation E1 for soft erasure and the second operation E2 foradditional erasure. Hence, the erase state can be made uniform. In otherwords, an excessively deep erase state (the state with an excessivelylow threshold voltage) can be suppressed. Thus, the state before writingcan be made uniform, which facilitates writing and can improvecontrollability in the write operation.

For instance, in a comparative example in which the erase operation EPis performed only by a single operation (e.g., first operation E1), theerase voltage needs to be excessively increased in order to form theerase state irrespective of the characteristics variation among aplurality of memory transistors MT. An excessively high erase voltagecauses excessively deep erasure, and some memory transistors MT may falloutside the desired threshold voltage. Furthermore, under an excessivelyhigh erase voltage, holes cg2 b may be captured by traps at shallowenergy levels at the interface between the semiconductor pillar SP andthe inner insulating film 42 and in the portion of the inner insulatingfilm 42 on the semiconductor pillar SP side and may degrade retentioncharacteristics. Furthermore, erroneous write may occur due to theso-called back tunneling by which electrons are injected into the memorylayer 48 (first memory layer 48 a and second memory layer 48 b) via theouter insulating film 43 (first outer insulating film 43 a and secondouter insulating film 43 b), for instance. Furthermore, an excessivestress is applied to the memory transistor MT, and it may causereliability degradation.

In contrast, according to this embodiment, the erase operation EPincludes a combination of the first operation E1 for soft erasure andthe second operation E2 for additional erasure. Hence, the excessivelydeep erasure does not occur, and the threshold voltage can be madeuniform. This facilitates write operation. Furthermore, holes cg2 b aresuppressed from being captured by traps at shallow energy levels, whichimproves retention characteristics and stabilizes the erase state.Furthermore, the back tunneling is suppressed, and erroneous write issuppressed. Furthermore, stress on the memory transistor MT is reduced,thereby improving reliability.

As described above, the memory unit MU further includes a select gate SGstacked on the multilayer structure ML in the first direction (Z-axisdirection) and pierced by one end of the semiconductor pillar SP. Thecontrol unit CTU sets, during the first period TE1 of the firstoperation E1, the select gate SG at the fifth potential V05, which islower than the first potential V01 and higher than the second potentialV02, and sets, during the second period TE2 of the second operation E2,the select gate SG at the sixth potential V06, which is lower than thethird potential V03 and higher than the fourth potential V04. Thus, GIDLis generated to perform the erase operation EP.

In the following, a description is given of an example in which thelength of the second period TE2 of the second operation E2 is shorterthan the length of the first period TE1 of the first operation E1 andthe difference between the third potential V03 and the fourth potentialV04 is equal to the difference between the first potential V01 and thesecond potential V02. A nonvolatile semiconductor memory device 111 inwhich this operation is performed is the same in configuration as thenonvolatile semiconductor memory device 110, but different in theoperation of the control unit CTU.

FIGS. 9A to 9D are schematic diagrams illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment.

More specifically, FIGS. 9A and 9B are a schematic diagram and a graph,respectively, illustrating the state of potential in the first operationE1. FIGS. 9C and 9D are a schematic diagram and a graph, respectively,illustrating the state of potential in the second operation E2. In FIGS.9B and 9D, the horizontal axis represents time t, and the vertical axisrepresents potential Vp.

FIGS. 10A to 10C are schematic diagrams illustrating the operation ofthe alternative nonvolatile semiconductor memory device according to thefirst embodiment.

More specifically, FIGS. 10A, 10B, and 10C show, in the first operationE1 and the second operation E2, the potential of the first wiring W1(the potential VSL of the source line SL) and the potential of thesecond wiring W2 (the potential VBL of the bit line BL); the potentialVSGD of the drain side select gate SGD and the potential VSGS of thesource side select gate SGS; and the potential VWL of the electrode filmWL, respectively.

As shown in FIGS. 9A and 9B, in the nonvolatile semiconductor memorydevice 111, the control unit CTU sets the wiring WR (e.g., first wiringW1 and second wiring W2) at a first potential V01 and the electrode filmWL at a second potential V02 lower than the first potential V01.

For instance, as shown in FIGS. 10A to 10C, during the first period TE1of the first operation E1, the first erase voltage Vera1 applied to thewiring WR rises from the reference potential V00 at time t11, reachesthe first potential V01 at time t13, then keeps the first potential V01until time t14, starts falling at time t14, and returns to the referencepotential V00 at time t16. The period from time t13 to time t14 is thefirst period TE1.

The first erase-time select gate voltage VeraG1 applied to the sourceside select gate SGS and the drain side select gate SGD rises from thereference potential V00 at time t12, reaches a fifth potential V05 attime t13, then keeps the fifth potential V05 until time t14, startsfalling at time t14, and returns to the reference potential V00 at timet15. Again, it is noted that the time of reaching the fifth potentialV05 and the time of starting falling from the fifth potential V05 may bedifferent from the time t13 of reaching the first potential V01 and thetime t14 of starting falling from the first potential V01.

In the first operation E1, the potential of the electrode film WL andthe back gate BG is constant at the second potential V02 (referencepotential V00).

The first potential V01 is illustratively 20 V, the fifth potential V05is illustratively 15 V, and the second potential V02 (referencepotential V00) is illustratively 0 V.

Time t12 comes after time t11, time t13 comes after time t12, time t14comes after time t13, time t15 comes after time t14, and time t16 comesafter time t15.

The first erase voltage Vera1 is not less than the first erase-timeselect gate voltage VeraG1 at any time.

Thus, GIDL is generated, and holes are injected into the memory layer 48(first memory layer 48 a and second memory layer 48 b) of the memorytransistor MT.

Here, again, the first erase voltage Vera1 is set to a voltage such thatthe threshold voltage of the memory transistor MT is slightly higherthan the target value of the erase state. For instance, when the targetthreshold voltage is −2 V, the threshold voltage of the memorytransistor MT is set to approximately −1 V.

Subsequently, as shown in FIGS. 9C and 9D, in the second operation E2,the control unit CTU sets the wiring WR (e.g., first wiring W1 andsecond wiring W2) at a third potential V03 and the electrode film WL ata fourth potential V04 lower than the third potential V03. Here, it isassumed that the fourth potential V04 is equal to the second potentialV02. Furthermore, in this case, the difference between the thirdpotential V03 and the fourth potential V04 is equal to the differencebetween the first potential V01 and the second potential V02. That is,the third potential V03 is equal to the first potential V01, or 20 V.

Furthermore, the period for which the third potential V03 (equal to thefirst potential V01 in this case) is applied in the second operation E2is shorter than the period for which the first potential V01 is appliedin the first operation E1.

For instance, as shown in FIGS. 10A to 10C, in the second operation E2,the second erase voltage Vera2 rises from the reference potential V00 attime t21, reaches the third potential V03 at time t23, then keeps thethird potential V03 until time t24, starts falling at time t24, andreturns to the reference potential V00 at time t26. In this example, theperiod from time t23 to time t24 is the second period TE2. The length ofthe second period TE2 is shorter than the length of the first periodTE1.

Also in this case, the second erase-time select gate voltage VeraG2rises from the reference potential V00 at time t22, reaches a sixthpotential V06 at time t23, then keeps the sixth potential V06 until timet24, starts falling at time t24, and returns to the reference potentialV00 at time t25. Again, the time of reaching the sixth potential V06 andthe time of starting falling from the sixth potential V06 may bedifferent from the time t23 of reaching the third potential V03 and thetime t24 of starting falling from the third potential V03.

In the second operation E2, the potential of the electrode film WL andthe back gate BG is constant at the fourth potential V04, which is equalto the second potential V02, or the reference potential V00.

The third potential V03 is equal to the first potential V01, such as 20V. The sixth potential V06 is equal to the fifth potential V05, such as15 V.

Time t22 comes after time t21, time t23 comes after time t22, time t24comes after time t23, time t25 comes after time t24, and time t26 comesafter time t25.

The second erase voltage Vera2 is not less than the second erase-timeselect gate voltage VeraG2 at any time.

Thus, GIDL is generated, and holes are injected into the memory layer 48(first memory layer 48 a and second memory layer 48 b) of the memorytransistor MT.

As described above, the first period TE1 for which the first operationE1 is performed is set to the period for which the first erase voltageVera1 is the first potential V01. Furthermore, the second period TE2 forwhich the second operation E2 is performed is set to the period forwhich the second erase voltage Vera2 is the third potential V03 (equalto the first potential V01 in this example). The second period TE2 isshorter than the first period TE1.

By this second operation E2, the threshold voltage, which has been setslightly higher by the first operation E1, is slightly lowered and setto the target value. That is, the threshold voltage of the memorytransistor MT is set to the target threshold value, such as −2 V.

The foregoing has described the example in which the length of thesecond period TE2 of the second operation E2 is equal to the length ofthe first period TE1 of the first operation E1 whereas the differencebetween the third potential V03 and the fourth potential V04 is smallerthan the difference between the first potential V01 and the secondpotential V02 and the example in which the length of the second periodTE2 of the second operation E2 is shorter than the length of the firstperiod TE1 of the first operation E1 whereas the difference between thethird potential V03 and the fourth potential V04 is equal to thedifference between the first potential V01 and the second potential V02.However, it is only necessary to satisfy at least one of: the length ofthe second period TE2 of the second operation E2 being shorter than thelength of the first period TE1 of the first operation E1; and thedifference between the third potential V03 and the fourth potential V04being smaller than the difference between the first potential V01 andthe second potential V02.

In the nonvolatile semiconductor memory device according to thisembodiment, the control unit CTU can further perform a verify readoperation as described below.

FIGS. 11A and 11B are flow charts illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment.

As shown in FIG. 11A, between the first operation E1 (step S110) and thesecond operation E2 (step S120), an alternative nonvolatilesemiconductor memory device 112 according to this embodiment performs athird operation E3 (step S130) for reading the threshold voltage of thememory transistor MT formed at the intersection between thesemiconductor pillar SP and the electrode film WL.

The configuration of the nonvolatile semiconductor memory device 112 canbe the same as that of the nonvolatile semiconductor memory devices 110and 111, and hence the description thereof is omitted.

The third operation E3 is the so-called verify read operation.

In the third operation E3, for instance, the first wiring W1 (sourceline SL) is set at a second potential V02 (e.g., 0 V), the second wiringW2 (bit line BL) is set at a low potential Vcc (e.g., approximately 3V), the first select gate SG1 and the second select gate SG2 are set atthe low potential Vcc, and the electrode film WL is set at a searchpotential Vse. Then, with the search potential Vse varied (that is, withthe potential of the electrode film WL varied between the firstpotential V01 and the second potential V02), the threshold voltage ofthe memory transistor MT corresponding to each electrode film WL isread. This operation is also performed by the control unit CTU.

Then, if the threshold voltage of the memory transistor MT read by thethird operation E3 has not reached the target value, the processproceeds to the second operation E2, and if the threshold voltage hasreached the target value, the process is completed (step S131).

When the threshold voltage has not reached the target value, the secondoperation E2 (step S120) is performed.

Thus, in this example, the second operation E2 is performed on the basisof the state of the threshold voltage of the memory transistor MT afterthe first operation E1. Thus, in the erase operation EP, the controlunit CTU performs an operation including the execution of the firstoperation E1 and the execution of the second operation E2.

Thus, the second operation E2 can be performed as needed, and the eraseoperation EP can be performed efficiently.

As shown in FIGS. 11B, in a nonvolatile semiconductor memory device 113according to this embodiment, a third operation E3 a (step S130 a) forreading the threshold voltage of the memory transistor MT formed at theintersection between the semiconductor pillar SP and the electrode filmWL is performed after the second operation E2.

The configuration of the nonvolatile semiconductor memory device 113 canbe the same as that of the nonvolatile semiconductor memory devices 110and 111, and hence the description thereof is omitted.

The third operation E3 a is also the verify read operation. In the thirdoperation E3 a, an operation similar to the aforementioned thirdoperation E3 is performed.

If the threshold voltage of the memory transistor MT read by the thirdoperation E3 a has not reached the target value, the process returns tothe second operation E2, and if the threshold voltage has reached thetarget value, the process is completed (step S131 a). Then, theaforementioned step S120, step S130 a, and step S131 a are repeateduntil the threshold voltage reaches the target value.

In this example, between the first operation E1 (step S110) and thesecond operation E2 (step S120), the aforementioned third operation E3(step S130) is performed. If the threshold voltage of the memorytransistor MT read by the third operation E3 has not reached the targetvalue, the process proceeds to the second operation E2, and if thethreshold voltage has reached the target value, the process is completed(step S131).

Then, after the second operation E2, the aforementioned step S130 a andstep S131 a are performed.

More specifically, the third operation E3 a is performed after thesecond operation E2. During a third period after the third operation E3a, the control unit CTU performs an operation (corresponding to a secondadditional erasure) for setting the first wiring W1 at an eighthpotential and setting the electrode film WL at a ninth potential lowerthan the eighth potential. Here, at least one of the following issatisfied: the length of the third period being shorter than the lengthof the second period; and the difference between the eighth potentialand the ninth potential being smaller than the difference between thethird potential V03 and the fourth potential V04.

The ninth potential is illustratively equal to the fourth potential V04,that is, equal to the second potential V02.

However, the invention is not limited thereto. It is also possible toomit step S130 and step S131, perform step S110 and step S120, thenperform step S130 a and step S131 a, repeating the aforementioned stepS120, step S130 a, and step S131 a until the threshold voltage reachesthe target value.

That is, the third operation E3 (or third operation E3 a) can beperformed at least one of between the first operation El and the secondoperation E2 and after the second operation E2.

Thus, the second operation E2 can be repeated as needed, and the eraseoperation EP can be performed efficiently.

In the case of repeating the second operation E2, at least one of thesecond period TE2 of the second operation E2 and the difference betweenthe third potential V03 and the fourth potential V04 may be varied withthe number of repetitions. Thus, the erase operation EP can be performedmore efficiently.

FIGS. 12A to 12D are schematic diagrams illustrating the operation of analternative nonvolatile semiconductor memory device according to thefirst embodiment.

More specifically, FIGS. 12A and 12B are a schematic diagram and agraph, respectively, illustrating the state of potential in the firstoperation E1. FIGS. 12C and 12D are a schematic diagram and a graph,respectively, illustrating the state of potential in the secondoperation E2. In FIGS. 12B and 12D, the horizontal axis represents timet, and the vertical axis represents potential Vp.

As shown in FIGS. 12A to 12D, in the operation of an alternativenonvolatile semiconductor memory device 114 according to thisembodiment, an erase voltage (first erase voltage Vera1) is applied tothe first wiring W1 (source line SL), but the second wiring W2 (bit lineBL) is set in the floating state FLT. Here, an erase-time select gatevoltage (first erase-time select gate voltage VeraG1) is applied to thefirst select gate SG1 (source side select gate SGS), but the secondselect gate SG2 (drain side select gate SGD) on the second wiring W2side is set in the floating state FLT.

More specifically, the memory unit MU further includes a secondsemiconductor pillar SP2 provided adjacent to the first semiconductorpillar SP1 in the second direction (Y-axis direction) orthogonal to thefirst direction (Z-axis direction) and piercing the multilayer structureML in the first direction, a second memory layer 48 b provided betweeneach electrode film WL and the second semiconductor pillar SP2, a secondinner insulating film 42 b provided between the second memory layer 48 band the second semiconductor pillar SP2, a second outer insulating film43 b provided between each electrode film WL and the second memory layer48 b, a second wiring W2 electrically connected to one end (second end)of the second semiconductor pillar SP2, a connecting portion CP (firstconnecting portion CP1) electrically connecting the other end (thirdend) opposite to the one end (first end) of the first semiconductorpillar SP1 and the other end (fourth end) opposite to the one end(second end) of the second semiconductor pillar SP2, a first select gateSG1 provided between the one end (first end) of the first semiconductorpillar SP1 and the multilayer structure ML and pierced by the firstsemiconductor pillar SP1, and a second select gate SG2 provided betweenthe one end (second end) of the second semiconductor pillar SP2 and themultilayer structure ML and pierced by the second semiconductor pillarSP2.

During the first period TE1 of the first operation E1, the control unitCTU sets the first wiring W1 at a first potential V01, the second wiringW2 in the floating state FLT, and the electrode film WL at a secondpotential V02 lower than the first potential V01.

Then, during the second period TE2 of the second operation E2 after thefirst operation E1, the control unit CTU sets the first wiring W1 at athird potential V03, the second wiring W2 in the floating state FLT, andthe electrode film WL at a fourth potential V04 lower than the thirdpotential V03.

Furthermore, during the first period TE1 of the first operation E1, thefirst select gate SG1 is set at a fifth potential V05, which is lowerthan the first potential V01 and higher than the second potential V02.Here, the second select gate SG2 is preferably set in the floating stateFLT.

Then, during the second period TE2 of the second operation E2, the firstselect gate SG1 is set at a sixth potential V06, which is lower than thethird potential V03 and higher than the fourth potential V04. Here, thesecond select gate SG2 is preferably set in the floating state FLT.

Thus, if the erase voltage (first erase voltage Vera1 and second erasevoltage Vera2) and the erase-time select gate voltage (first erase-timeselect gate voltage VeraG1 and second erase-time select gate voltageVeraG2) are applied, respectively, to the first wiring W1 and the firstselect gate SG1 corresponding to one end of a memory string, then thesecond wiring W2 and the second select gate SG2 corresponding to theother end of the memory string may be in the floating state FLT.

Second Embodiment

FIGS. 13A to 13D are schematic diagrams illustrating the operation of anonvolatile semiconductor memory device according to a secondembodiment.

More specifically, FIGS. 13A and 13B are a schematic diagram and agraph, respectively, illustrating the state of potential in the firstoperation E1. FIGS. 13C and 13D are a schematic diagram and a graph,respectively, illustrating the state of potential in the secondoperation E2. In FIGS. 13B and 13D, the horizontal axis represents timet, and the vertical axis represents potential Vp.

In this embodiment, the second operation E2 does not necessarily need tobe performed as a combination with the first operation E1 after thefirst operation E1, but the first operation E1 and the second operationE2 may be performed independently.

As shown in FIG. 13A, in a nonvolatile semiconductor memory device 120according to this embodiment, the control unit CTU sets the wiring WR(e.g., first wiring W1 and second wiring W2) at a first potential V01when performing at least one operation of: injection of holes into onememory layer 48 (one memory section, selected memory layer 48) of aplurality of memory layers 48; and extraction of electrons from the onememory layer 48 (the one memory section, selected memory layer 48).

Furthermore, the electrode film WL opposed to the one memory layer 48(the one memory section) is set at a second potential V02 lower than thefirst potential V01, and the electrode films WL opposed to the memorylayers 48 (memory section) except the one memory layer 48 (the onememory section) are set in the floating state FLT.

In this example, the electrode films WL0S, WL1S, WL0D, and WL1D opposedto the selected memory layers 48 are grounded to the reference potentialV00, which is the second potential V02, and the electrode films WL2S,WL3S, WL2D, and WL3D opposed to the other memory layers 48 are set inthe floating state FLT.

By this operation, a memory transistor MT corresponding to a particularelectrode film WL can be selectively erased. In this example, the memorytransistors MT corresponding to the electrode films WL0S, WL1S, WL0D,and WL1D are selectively erased.

On the other hand, because the electrode films WL2S, WL3S, WL2D, andWL3D are set in the floating state FLT, these electrode films WL areboosted by capacitive coupling. Hence, no potential difference occursbetween the electrode films WL and the wiring WR. Thus, erasure is notperformed in the memory transistors MT corresponding to these electrodefilms WL.

Here, at least one of the erase voltage (first erase voltage Vera1) andthe length of the first period TE1 can be optimally adapted to thesememory transistors MT.

For instance, the size of the through hole TH provided in the multilayerstructure ML may be nonuniform depending on the distance from thesubstrate 11. For instance, in comparison between the lower portion(substrate-proximal portion) near the substrate 11 and the upper portion(substrate-distal portion) at farther distance from the substrate 11than the lower portion, the through hole TH in the upper portion mayhave a larger diameter, and hence a larger curvature radius. In thiscase, a relatively larger potential difference is applied between thewiring WR and the electrode film WL to erase the memory transistor MT inthe upper portion than in the lower portion. By using an optimal erasevoltage in each of the upper portion and the lower portion, each memorytransistor MT can be set in a suitable erase state.

For instance, the first potential V01, which is the maximum of the firsterase voltage Vera1, is illustratively 20 V, and the second potentialV02 is the reference potential V00, or the ground potential GND (0 V).

Here, the setting of the potential of the first select gate SG1 and thesecond select gate SG2 (fifth potential V05, or first erase-time selectgate voltage VeraG1) can be the same as that described with reference toFIGS. 6A to 6D, and hence the description thereof is omitted.

By using the voltage as described above, only the desired memorytransistor MT can be erased by an optimal erase voltage. Thus, the erasestate can be made uniform, which can improve controllability in thesubsequent write operation, for instance. Furthermore, this improvesretention characteristics, stabilizes the erase state, and alsosuppresses erroneous write. Furthermore, selective erasure of only thedesired memory transistor MT serves to improve reliability andaccelerate the erase operation.

In the second operation E2 shown in FIG. 13C, the electrode films WL2S,WL3S, WL2D, and WL3D are grounded to the reference potential V00, whichis the fourth potential V04, and the electrode films WL0S, WL1S, WL0D,and WL1D opposed to the other memory layers 48 are set in the floatingstate FLT.

By this operation, the memory transistors MT corresponding to theelectrode films WL2S, WL3S, WL2D, and WL3D are selectively erased.

Here, at least one of the erase voltage (second erase voltage Vera2) andthe length of the second period TE2 can be optimally adapted to thesememory transistors MT.

The third potential V03, which is the maximum of the second erasevoltage Vera2, is illustratively 19 V, and the fourth potential V04 isthe reference potential V00, or the ground potential GND (0 V).

Here, the setting of the potential of the first select gate SG1 and thesecond select gate SG2 (sixth potential V06, or the maximum of thesecond erase-time select gate voltage VeraG2) can be the same as thatdescribed with reference to FIGS. 6A to 6D, and hence the descriptionthereof is omitted.

By using the voltage as described above, only the desired memorytransistor MT can be erased by an optimal erase voltage. Thus, the erasestate can be made uniform, which can improve controllability in thesubsequent write operation, for instance. Furthermore, this improvesretention characteristics, stabilizes the erase state, and alsosuppresses erroneous write. Furthermore, selective erasure serves toimprove reliability and accelerate the erase operation.

Thus, in a selective first erase operation EP on a first selected memorylayer 48 (one memory layer 48 of a plurality of memory layers 48, memorysection), during the first period TE1, the control unit CTU performs afirst operation E1 for setting the wiring WR (first wiring W1 and secondwiring W2) at a first potential V01, setting the electrode film WLopposed to the first selected memory layer 48 at a second potential V02lower than the first potential V01, and setting the electrode film WLopposed to first non-selected memory layers 48 (the memory layers 48except the first selected memory layer 48, memory section) in thefloating state FLT. Furthermore, during the second period TE2 (e.g.,after the first period TE1), in a selective second erase operation EP ona second selected memory layer 48 (another memory layer 48 of aplurality of memory layers 48, memory sections) other than the firstselected memory layer 48 (the memory section), the control unit CTU canperform a second operation E2 for setting the wiring WR (first wiring W1and second wiring W2) at a third potential V03, setting the electrodefilm WL opposed to the second selected memory layer 48 (the memorysection) at a fourth potential V04 lower than the third potential V03,and setting the electrode film WL opposed to second non-selected memorylayers 48 (the memory layers 48 except the second selected memory layer48, the memory section)) in the floating state FLT.

Furthermore, at least one of the following may be satisfied: the lengthof the second period TE2 being different from the length of the firstperiod TE1; and the difference between the third potential V03 and thefourth potential V04 being different from the difference between thefirst potential V01 and the second potential V02.

Hence, each desired memory transistor MT can be selectively erased by anoptimal erase voltage. Thus, the erase state can be made more uniform.

Furthermore, also in this case, as described with reference to FIG. 12,in the first operation E1, with the first wiring W1 set at a firstpotential V01, the second wiring W2 can be set in the floating stateFLT, and with the first select gate SG1 set at a fifth potential V05,the second select gate SG2 can be set in the floating state FLT.Furthermore, in the second operation E2, with the first wiring W1 set ata third potential V03, the second wiring W2 can be set in the floatingstate FLT, and with the first select gate SG1 set at a sixth potentialV06, the second select gate SG2 can be set in the floating state FLT.

Third Embodiment

FIGS. 14A to 14F are schematic diagrams illustrating the operation of anonvolatile semiconductor memory device according to a third embodiment.

More specifically, FIG. 14A is a schematic diagram illustrating thestate of potential in a nonvolatile semiconductor memory device 130.FIGS. 14B to 14F are graphs illustrating the state of potential, whereFIG. 14B shows the erase voltage Vera and the erase-time select gatevoltage VeraG, and FIGS. 14C to 14F show, respectively, the applicationvoltage VWL3 to the electrode films WL3S and WL3D, the applicationvoltage VWL2 to the electrode films WL2S and WL2D, the applicationvoltage VWL1 to the electrode films WL1S and WL1D, and the applicationvoltage VWL0 to the electrode films WL0S and WL0D.

As shown in FIGS. 14A to 14F, the control unit CTU performs thefollowing process in the operation of performing at least one of:injection of holes into the memory layer 48; and extraction of electronsfrom the memory layer 48.

The control unit CTU sets the wiring WR (e.g., first wiring W1 andsecond wiring W2) at a first potential V01 and one electrode film WL ofa plurality of electrode films WL at a second potential V02 lower thanthe first potential V01. Furthermore, the control unit CTU sets anotherelectrode film WL of the plurality of electrode films WL at a seventhpotential V07, which is lower than the first potential V01 and differentfrom the second potential V02.

The first potential V01 is illustratively 20 V, and the second potentialV02 is illustratively the reference potential V00, or 0 V.

The erase voltage Vera, the erase-time select gate voltage VeraG, thefifth potential V05, the period TE, and time t11, t12, t13, t14, t15,and t16 illustrated in FIG. 14B can be the same as the first erasevoltage Vera1, the first erase-time select gate voltage VeraG1, thefifth potential V05, the first period TE1, and time t11, t12, t13, t14,t15, and t16 described with reference to FIGS. 6A to 6D, and hence thedescription thereof is omitted.

In the first operation E1 illustrated in FIGS. 6A to 6D, all theelectrode films WL are simultaneously set at the second potential V02.However, in the nonvolatile semiconductor memory device 130 according tothis embodiment, at least two of the electrode films WL are set atdifferent potentials.

For instance, the application voltage VWL3 to the electrode films WL3Sand WL3D is constant at the second potential V02 (reference potentialV00), or 0 V. The maximum of the application voltage VWL2 to theelectrode films WL2S and WL2D is illustratively 1 V. The maximum of theapplication voltage VWL1 to the electrode films WL1S and WL1D isillustratively 2 V. The maximum of the application voltage VWL0 to theelectrode films WL0S and WL0D is illustratively 3 V.

Each of the application voltages VWL0 to VWL2 rises from the referencepotential V00 at time t11, reaches the associated maximum potential (3V, 2 V, and 1 V) at time t13, then keeps the maximum potential untiltime t14, starts falling at time t14, and returns to the referencepotential V00 at time t16. In this example, the period from time t13 totime t14 is the period TE.

Thus, by setting the electrode films WL independently at differentpotentials, each memory transistor MT opposed to the associatedelectrode film WL can be optimally erased.

For instance, as described above, the size of the through hole THprovided in the multilayer structure ML may be nonuniform depending onthe distance from the substrate 11. For instance, as compared with thelower portion (substrate-proximal portion) near the substrate 11, thethrough hole TH may have a larger diameter, and hence a larger curvatureradius, in the upper portion (substrate-distal portion) at fartherdistance from the substrate 11 than the lower portion. In this case,while the erase voltage Vera applied to the wiring WR is left constant,the electrode film WL in the upper portion having a relatively largercurvature radius is set at 0 V, and the electrode film WL in the lowerportion having a relatively smaller curvature radius is set at a voltagehigher than 0 V, for instance

More specifically, a first region (e.g., substrate-distal portion, orupper portion) where the outer insulating film 43 has a large outerdiameter along the second direction (Y-axis direction) perpendicular tothe first direction (Z-axis direction), and a second region (e.g.,substrate-proximal portion, or lower portion) where the outer diameteralong the second direction is smaller than in the first region, aredefined. The aforementioned one electrode film WL of a plurality ofelectrode films WL is an electrode film WL in the first region, and theaforementioned other electrode film WL of the plurality of electrodefilms WL is an electrode film WL in the second region. Here, the seventhpotential V07 is illustratively 1 V to 3 V, which is higher than thesecond potential V02 (e.g., 0 V).

That is, as illustrated in FIGS. 14A to 14F, the maximum of theapplication voltage VWL0 to the electrode film WL0S and the electrodefilm WL0D, for instance, corresponding to the memory transistors MT inthe lower portion is set higher than the maximum of the applicationvoltage VWL3 to the electrode film WL3S and the electrode film WL3Dcorresponding to the memory transistors MT in the upper portion so thatoptimal potential differences are respectively applied to the memorytransistors MT in the upper portion and the lower portion. Thus, each ofthe memory transistors MT can be set at a suitable erase state.

Also in this case, as described with reference to FIGS. 12A to 12D, withthe first wiring W1 set at a first potential V01, the second wiring W2can be set in the floating state FLT, and with the first select gate SG1set at a fifth potential V05, the second select gate SG2 can be set inthe floating state FLT.

It is noted that various operations described with reference to thefirst to third embodiments may be suitably combined. For instance, thesecond embodiment and the third embodiment can be combined. Then, thememory transistors MT opposed to different electrode films WL can beseparately erased by varying the erase voltage Vera and further varyingthe potential VWL depending on the electrode film WL.

Fourth Embodiment

FIGS. 15 and 16 are a schematic cross-sectional view and a schematicperspective view, respectively, illustrating the configuration of anonvolatile semiconductor memory device according to a fourthembodiment.

It is noted that for clarity of illustration, FIG. 16 shows only theconductive portions and omits the insulating portions.

As shown in FIGS. 15 and 16, a nonvolatile semiconductor memory device140 according to this embodiment also includes a memory unit MU and acontrol unit CTU.

In the memory unit MU, semiconductor pillars SP are not connected in aU-shape, but are independent of each other. That is, the nonvolatilesemiconductor memory device 140 includes linear NAND strings. An upperselect gate USG (second select gate SG2, illustratively serving as adrain side select gate SGD) is provided above the multilayer structureML, and a lower select gate LSG (first select gate SG1, illustrativelyserving as a source side select gate SGS) is provided below themultilayer structure ML.

An upper select gate insulating film USGI illustratively made of siliconoxide is provided between the upper select gate USG and thesemiconductor pillar SP, and a lower select gate insulating film LSGIillustratively made of silicon oxide is provided between the lowerselect gate LSG and the semiconductor pillar SP.

Furthermore, a source line SL (first wiring W1, which is one of thewirings WR) is provided below the lower select gate LSG. An interlayerinsulating film 13 a is provided below the source line SL, and aninterlayer insulating film 13 b is provided between the source line SLand the lower select gate LSG.

The semiconductor pillar SP is connected to the source line SL below thelower select gate LSG and to a bit line BL (second wiring W2, which isone of the wirings WR) above the upper select gate USG. Thus, memorytransistors MT (memory cells MC) are formed in the multilayer structureML between the upper select gate USG and the lower select gate LSG, andthe semiconductor pillar SP functions as one linear memory string. Thismemory string is illustratively a NAND string.

The upper select gate USG and the lower select gate LSG are divided inthe Y-axis direction by an interlayer insulating film 17 and aninterlayer insulating film 13 c, respectively, and shaped like stripsaligning in the X-axis direction.

On the other hand, the bit line BL connected to the upper portion of thesemiconductor pillar SP and the source line SL connected to the lowerportion of the semiconductor pillar SP are shaped like strips aligningin the Y-axis direction.

In this case, the electrode film WL is a plate-like conductive filmparallel to the X-Y plane.

Also in the nonvolatile semiconductor memory device 140 having such astructure, the control unit CTU performs the operation described withreference to the first to third embodiments. Thus, a stable erase statecan be realized.

In the nonvolatile semiconductor memory device according to theembodiments of the invention, the interelectrode insulating film 14, theinner insulating film 42, and the outer insulating film 43 can be amonolayer film made of a material selected from the group includingsilicon oxide, silicon nitride, silicon oxynitride, aluminum oxide,aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafniumnitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanumoxide, and lanthanum aluminate, or a multilayer film made of a pluralityof materials selected from the group.

The memory layer 48 can be a monolayer film made of a material selectedfrom the group including silicon nitride, silicon oxynitride, aluminumoxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride,hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate,lanthanum oxide, and lanthanum aluminate, or a multilayer film made of aplurality of materials selected from the group.

In the specification of the application, “perpendicular” and “parallel”refer to not only strictly perpendicular and strictly parallel but alsoinclude, for instance, the fluctuation due to manufacturing processes,etc. It is sufficient to be substantially perpendicular andsubstantially parallel. The embodiments of the invention have beendescribed with reference to examples. However, the invention is notlimited to these examples. For instance, various specific configurationsof the components, such as the substrate, electrode film, insulatingfilm, insulating layer, multilayer structure, memory layer, chargestorage layer, semiconductor pillar, word line, bit line, source line,wiring, memory transistor, and select gate transistor constituting thenonvolatile semiconductor memory device are encompassed within the scopeof the invention as long as those skilled in the art can similarlypractice the invention and achieve similar effects by suitably selectingsuch configurations from conventionally known ones.

Furthermore, any two or more components of the examples can be combinedwith each other as long as technically feasible, and such combinationsare also encompassed within the scope of the invention as long as theyfall within the spirit of the invention.

Furthermore, those skilled in the art can suitably modify and implementthe nonvolatile semiconductor memory device described above in theembodiments of the invention, and all the nonvolatile semiconductormemory devices thus modified are also encompassed within the scope ofthe invention as long as they fall within the spirit of the invention.

Furthermore, those skilled in the art can conceive various modificationsand variations within the spirit of the invention, and it is understoodthat such modifications and variations are also encompassed within thescope of the invention. For instance, those skilled in the art cansuitably modify the above embodiments by addition, deletion, or designchange of components, or by addition, omission, or condition change ofprocesses, and such modifications are also encompassed within the scopeof the invention as long as they fall within the spirit of theinvention.

1. A nonvolatile semiconductor memory device comprising: a memory unit;and a control unit, the memory unit including: a multilayer structureincluding a plurality of electrode films and a plurality ofinterelectrode insulating films alternately stacked in a firstdirection; a first semiconductor pillar piercing the multilayerstructure in the first direction; a first memory layer provided betweeneach of the electrode films and the first semiconductor pillar; a firstinner insulating film provided between the first memory layer and thefirst semiconductor pillar; a first outer insulating film providedbetween each of the electrode films and the first memory layer; and afirst wiring electrically connected to one end of the firstsemiconductor pillar, the control unit performing: a first operationsetting the first wiring at a first potential and setting the electrodefilm at a second potential lower than the first potential during a firstperiod; and an operation including a second operation setting the firstwiring at a third potential and setting the electrode film at a fourthpotential lower than the third potential during a second period afterthe first operation, the operation including the second operation havingat least one of: a length of the second period being shorter than alength of the first period; and a difference between the third potentialand the fourth potential being smaller than a difference between thefirst potential and the second potential, the first operation and theoperation including the second operation being performed in an operationfor performing at least one of injection of holes into the first memorylayer and extraction of electrons from the first memory layer.
 2. Thedevice according to claim 1, wherein the control unit performs a thirdoperation reading a threshold voltage of a memory transistor formed atan intersection between the first semiconductor pillar and the electrodefilm at least one of after the second operation and between the firstoperation and the second operation.
 3. The device according to claim 2,wherein the third operation is performed after the second operation, thecontrol unit performs an operation setting the first wiring at an eighthpotential and setting the electrode film at a ninth potential lower thanthe eighth potential during a third period after the third operation,and the operation preformed during the third period includes at leastone of: a length of the third period being shorter than the length ofthe second period; and a difference between the eighth potential and theninth potential being smaller than the difference between the thirdpotential and the fourth potential.
 4. The device according to claim 1,wherein the memory unit further includes a select gate stacked on themultilayer structure in the first direction and pierced by the one endof the semiconductor pillar, and the control unit sets: the select gateat a fifth potential during the first period, the fifth potential beinglower than the first potential and higher than the second potential; andthe select gate at a sixth potential during the second period, the sixthpotential being lower than the third potential and higher than thefourth potential.
 5. The device according to claim 4, wherein adifference between the fifth potential and the second potential and adifference between the sixth potential and the second potential arelower than a breakdown voltage of a select gate transistor of the selectgate.
 6. The device according to claim 4, wherein a potential of theselect gate starts changing from the second potential to the fifthpotential after a time when a potential of the first wiring startschanging from the second potential to the first potential during thefirst period, and the potential of the select gate finishes changingfrom the fifth potential to the second potential after the time when thepotential of the first wiring finishes changing from the first potentialto the second potential during the second period.
 7. The deviceaccording to claim 4, wherein the control unit performs a thirdoperation reading a threshold voltage of a memory transistor formed atan intersection between the first semiconductor pillar and the electrodefilm at least one of after the second operation and between the firstoperation and the second operation and, and the control unit sets thefirst wiring at the second potential, sets the select gate at apotential being lower than the first potential and higher than thesecond potential, and reads the threshold voltage of the memorytransistor with the potential of the electrode film varied between thefirst potential and the second potential in the third operation.
 8. Thedevice according to claim 1, wherein the memory unit further includes: asecond semiconductor pillar provided adjacent to the first semiconductorpillar in a second direction orthogonal to the first direction andpiercing the multilayer structure in the first direction; a secondmemory layer provided between each of the electrode films and the secondsemiconductor pillar; a second inner insulating film provided betweenthe second memory layer and the second semiconductor pillar; a secondouter insulating film provided between each of the electrode films andthe second memory layer; a second wiring electrically connected to oneend of the second semiconductor pillar; and a connecting portionelectrically connecting between another end opposite to the one end ofthe first semiconductor pillar and another end opposite to the one endof the second semiconductor pillar, the control unit sets: the secondwiring in a floating state during the first period of the firstoperation; and the second wiring in the floating state during the secondperiod of the second operation.
 9. The device according to claim 1,wherein the memory unit further includes: a second semiconductor pillarprovided adjacent to the first semiconductor pillar in a seconddirection orthogonal to the first direction and piercing the multilayerstructure in the first direction; a second memory layer provided betweeneach of the electrode films and the second semiconductor pillar; asecond inner insulating film provided between the second memory layerand the second semiconductor pillar; a second outer insulating filmprovided between each of the electrode films and the second memorylayer; a second wiring electrically connected to one end of the secondsemiconductor pillar; a connecting portion electrically connectingbetween another end opposite to the one end of the first semiconductorpillar and another end opposite to the one end of the secondsemiconductor pillar; a first select gate provided between the one endof the first semiconductor pillar and the multilayer structure andpierced by the first semiconductor pillar; and a second select gateprovided between the one end of the second semiconductor pillar and themultilayer structure and pierced by the second semiconductor pillar, thecontrol unit sets: the second wiring in a floating state; the firstselect gate at a fifth potential being lower than the first potentialand higher than the second potential; and the second select gate at thefifth potential or in the floating state, during the first period of thefirst operation, and the control unit sets: the second wiring in thefloating state; the first select gate at a sixth potential being lowerthan the third potential and higher than the fourth potential; and thesecond select gate at the sixth potential or in the floating state,during the second period of the second operation.
 10. The deviceaccording to claim 9, wherein a difference between the fifth potentialand the second potential is lower than a breakdown voltage of a selectgate transistor of the first select gate.
 11. The device according toclaim 10, wherein a difference between the sixth potential and thesecond potential is lower than the breakdown voltage of a select gatetransistor of the second select gate.
 12. The device according to claim9, wherein the control unit performs a third operation reading athreshold voltage of a memory transistor formed at an intersectionbetween the first semiconductor pillar and the electrode film at leastone of after the second operation and between the first operation andthe second operation
 13. The device according to claim 12, wherein thecontrol unit sets the first wiring at the second potential, sets thesecond wiring, the first select gate, and the second select gate at apotential being lower than the first potential and higher than thesecond potential, and reads the threshold voltage of the memorytransistor with the potential of the electrode film varied between thefirst potential and the second potential, in the third operation. 14.The device according to claim 1, wherein the memory layer includes amonolayer film made of a material selected from a first group includingsilicon nitride, silicon oxynitride, aluminum oxide, aluminumoxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitridealuminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide,and lanthanum aluminate, or a multilayer film made of a plurality ofmaterials selected from the first group.
 15. The device according toclaim 14, wherein at least one of the interelectrode insulating film,the inner insulating film, and the outer insulating film includes amonolayer film made of a material selected from a second group includingsilicon oxide, silicon nitride, silicon oxynitride, aluminum oxide,aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafniumnitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanumoxide, and lanthanum aluminate, or a multilayer film made of a pluralityof materials selected from the second group.
 16. A nonvolatilesemiconductor memory device comprising: a memory unit; and a controlunit, the memory unit including: a multilayer structure including aplurality of electrode films and a plurality of interelectrodeinsulating films alternately stacked in a first direction; asemiconductor pillar piercing the multilayer structure in the firstdirection; a memory layer provided between each of the electrode filmsand the semiconductor pillar; an inner insulating film provided betweenthe memory layer and the semiconductor pillar; an outer insulating filmprovided between each of the electrode films and the memory layer; and awiring electrically connected to one end of the semiconductor pillar,and the control unit setting: the wiring at a first potential; and theelectrode film opposed to one of memory sections of the memory layerfacing the plurality of electrode films at a second potential lower thanthe first potential and the electrode film opposed to the memory sectionexcept the one of memory sections in a floating state, the setting beingperformed in an operation for performing at least one of injection ofholes into the one memory section and extraction of electrons from theone memory section.
 17. The device according to claim 16, wherein theone memory section is a first selected memory section, the control unitsets: the wiring at the first potential, the electrode film opposed tothe first selected memory section at the second potential lower than thefirst potential, and the electrode film opposed to the memory sectionsexcept the first selected memory section in the floating state during afirst period in the operation for performing at least one of injectionof holes into the first selected memory section and extraction ofelectrons from the first selected memory section; and the wiring at athird potential, the electrode film opposed to a second selected memorysection at a fourth potential lower than the third potential, and theelectrode film opposed to the memory section except the second selectedmemory section in the floating state during a second period after thefirst period in an operation for performing at least one of injection ofholes into the second selected memory section of the plurality of memorysections other than the first selected memory section and extraction ofelectrons from the second selected memory section, the operationperformed during the second period including at least one of: a lengthof the second period being different from a length of the first period;and a difference between the third potential and the fourth potentialbeing different from a difference between the first potential and thesecond potential.
 18. The device according to claim 16, wherein thememory unit further includes: a second semiconductor pillar providedadjacent to the first semiconductor pillar in a second directionorthogonal to the first direction and piercing the multilayer structurein the first direction; a second memory layer provided between each ofthe electrode films and the second semiconductor pillar; a second innerinsulating film provided between the second memory layer and the secondsemiconductor pillar; a second outer insulating film provided betweeneach of the electrode films and the second memory layer; a second wiringelectrically connected to one end of the second semiconductor pillar; aconnecting portion electrically connecting between another end oppositeto the one end of the first semiconductor pillar and another endopposite to the one end of the second semiconductor pillar; a firstselect gate provided between the one end of the first semiconductorpillar and the multilayer structure and pierced by the firstsemiconductor pillar; and a second select gate provided between the oneend of the second semiconductor pillar and the multilayer structure andpierced by the second semiconductor pillar, the control unit setting:the second wiring in a floating state; the first select gate at a fifthpotential being lower than the first potential and higher than thesecond potential; and the second select gate at the fifth potential orin the floating state, during the first period of the first operation,and the control unit setting: the second wiring in the floating state;the first select gate at a sixth potential being lower than the thirdpotential and higher than the fourth potential; and the second selectgate at the sixth potential or in the floating state, during the secondperiod of the second operation.
 19. A nonvolatile semiconductor memorydevice comprising: a memory unit; and a control unit, the memory unitincluding: a multilayer structure including a plurality of electrodefilms and a plurality of interelectrode insulating films alternatelystacked in a first direction; a semiconductor pillar piercing themultilayer structure in the first direction; a memory layer providedbetween each of the electrode films and the semiconductor pillar; aninner insulating film provided between the memory layer and thesemiconductor pillar; an outer insulating film provided between each ofthe electrode films and the memory layer; and a wiring electricallyconnected to one end of the semiconductor pillar, and the control unitsetting: the wiring at a first potential one electrode film of theplurality of electrode films at a second potential lower than the firstpotential; and another electrode film of the plurality of electrodefilms at a seventh potential lower than the first potential anddifferent from the second potential, the setting being performed in anoperation for performing at least one of injection of holes into thememory layer and extraction of electrons from the memory layer.
 20. Thedevice according to claim 19, wherein the memory unit includes a firstregion and a second region, an outer diameter of the outer insulatingfilm along a second direction perpendicular to the first direction inthe first region is larger than an outer diameter of the outerinsulating film along the second direction in the second region, the oneelectrode film of the plurality of electrode films is an electrode filmin the first region, and the another electrode film of the plurality ofelectrode films is an electrode film in the second region, and theseventh potential is higher than the second potential.